1. Technical Field
Exemplary embodiments relate to a semiconductor memory device, and more particularly to a semiconductor memory device including a refresh control circuit and a memory system including the semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices may be classified into volatile memory devices and non-volatile memory devices according to whether stored information is retained when power to the semiconductor memory devices is off. Random access memory devices (RAM) are volatile memory devices which may be used as main memory devices for various devices such as personal computers. In dynamic RAM (DRAM), memory cells may include a transistor and a capacitor, and data “1” or “0” may be written by storing charge in the capacitor. Because the stored charge in the capacitor may decrease with time, the capacitors need to be periodically refreshed to maintain the data stored in them.
Memory cells in the DRAM are respectively connected to a corresponding word line and a corresponding bit line. In response to a word line enable signal, the transistors in the memory cells are turned on, and then stored charge is output to the bit line, or data provided through the bit line is stored in the capacitor.
Once charge is stored in the capacitor, the charge may be retained until a refresh period expires. After the refresh period expires, the written data may not be correctly identified since the stored charge decreases over time due to leakage current. The number of word lines (that is, rows) to be refreshed in the memory cell array may be referred to as a number of refresh cycles. A refresh interval may be obtained by dividing the refresh period by the number of refresh cycles.
Refresh operations performed in the DRAM may include auto refresh operations and self refresh operations. The auto refresh operations may be performed based on commands or control signals from the exterior of the semiconductor memory devices, and the self refresh operations may be performed based on oscillation signals generated by an internal oscillator included in semiconductor memory devices.
When the commands or control signals for performing the auto refresh operations are provided to the semiconductor memory devices through pins or pads, the configuration of a system including the semiconductor memory devices becomes complex, and access time to the semiconductor memory devices becomes great, thereby degrading overall performance of the system. Moreover, when the refresh operations are terminated before the refresh period expires, the semiconductor memory device unnecessarily performs the refresh operation again, and thus power consumption may be undesirably increased.